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vyges-vt-swap — threshold-voltage swapping

Part of the Vyges Loom suite (optimizer). Install once with vyges install loom, then run vyges loom vt-swap. It’s also a standalone vyges-vt-swap binary on your PATH.

The sibling of vyges-resize: same timer-scored cell-swap loop, but it trades threshold voltage (leakage/speed) instead of drive strength. A higher-Vt flavor of a gate is slower but leaks far less; a lower-Vt flavor is faster but leakier. Two objectives:

  • leakage (default) — on a timing-met design, push every cell with positive slack to the highest-Vt (lowest-leakage) flavor that still meets timing. Free leakage recovery.
  • timing — drop critical-path cells to a faster (lower-Vt) flavor to close setup.

It reports total cell leakage before and after (from the .lib’s cell_leakage_power) alongside the timing it preserved.

Run it

vyges install loom                                      # one-time: fetch the Loom suite
vyges loom vt-swap demo                                 # instant: built-in example recovers leakage
vyges loom vt-swap run  top.vtswap -o swapped.v         # swap → resized netlist
vyges loom vt-swap run  top.vtswap --json               # before/after timing + leakage
vyges loom vt-swap check top.vtswap                     # validate the job

A .vtswap job lists the iso-footprint Vt families fastest → slowest (low-Vt → high-Vt), plus objective: (leakage | timing), effort:, and dont_touch:.

See the full CLI reference (generated from --help).

Where it sits

netlist + .lib + constraints (+ optional .spef) → resized netlist + before/after WNS and leakage. Same footprint, so placement/routing are untouched. See the data spine.

Domain coverage

vyges-vt-swap trades standard-cell Vt flavors for leakage / setup, scored by the digital vyges-sta-si timer — it is digital optimization. It does not apply to analog / mixed-signal blocks, which have no iso-footprint Vt cell families and no Liberty-arc timing to score against. For analog / MS physical & integrity verification, see lvs (connectivity), layout (geometry), em-ir (IR / EM), thermal, and extract (RC).

Source & releases