vyges-sta-si — timing with signal integrity

Part of the Vyges Loom suite. Install once with vyges install loom, then run vyges loom sta-si. It’s also a standalone vyges-sta-si binary on your PATH (the integration contract for flow authors).

vyges-sta-si checks whether a design meets timing — reporting worst negative slack (WNS), total negative slack (TNS), and the critical path — while accounting for signal-integrity coupling between nets. It reads the .lib from vyges-char and the .spef from vyges-extract.

Run it

vyges install loom                                  # one-time: fetch the Loom suite
vyges loom sta-si demo                              # instant: built-in design → WNS/TNS
vyges loom sta-si run  top.sta -o top.rpt           # analyze → timing report
vyges loom sta-si run  top.sta --fail-on-violation  # exit 3 if WNS < 0 (CI gate)
vyges loom sta-si check top.sta                      # validate the job

See the full CLI reference (generated from --help).

Where it sits

.lib + .spef + design & constraints → WNS / TNS / worst path. Designed to gate CI: a timing violation returns a distinct non-zero exit code. See the data spine.

Domain coverage

vyges-sta-si builds a timing graph over Liberty cell arcs and propagates slews and arrivals through a clocked gate-level netlist — it is digital sign-off. It does not apply to analog / mixed-signal blocks, whose timing and behavior have no standard-cell or Liberty-arc analogue. For analog / MS physical & integrity verification, see lvs (connectivity), layout (geometry), em-ir (IR / EM), thermal, and extract (RC).

Source & releases

• Repo: https://github.com/vyges-tools/sta-si
• Binaries: https://github.com/vyges-tools/sta-si/releases
• Apache-2.0. Per-foundry calibration plugins are separate (NDA).