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vyges-resize — gate sizing

Part of the Vyges Loom suite (optimizer). Install once with vyges install loom, then run vyges loom resize. It’s also a standalone vyges-resize binary on your PATH.

Where the sign-off engines say what’s wrong, the optimizers fix it. vyges-resize picks a better drive strength for each cell — upsizing cells on the critical path to close setup violations, downsizing cells with slack to recover area — then emits the resized netlist. The logic never changes; only the cell variant does, and every candidate is scored by the vyges-sta-si timer. Run it pre-place (ideal interconnect) or as a post-place ECO by naming a spef: so sizing is scored against the real wire RC.

Run it

vyges install loom                                    # one-time: fetch the Loom suite
vyges loom resize demo                                # instant: built-in example closes a violation
vyges loom resize run  top.resize -o sized.v          # size → resized netlist
vyges loom resize run  top.resize --fail-on-violation # exit 3 if still violating (CI gate)
vyges loom resize check top.resize                    # validate the job

A .resize job is a superset of a .sta job plus group: (interchangeable cell families, weakest → strongest), objective: (timing | area), effort:, and dont_touch:.

See the full CLI reference (generated from --help).

Where it sits

netlist + .lib + constraints (+ optional .spef) → resized netlist + before/after WNS/TNS. It decides sizes, not locations — placement/routing stay the flow’s job. See the data spine.

Domain coverage

vyges-resize swaps standard-cell drive strengths, scored by the digital vyges-sta-si timer — it is digital optimization. It does not apply to analog / mixed-signal blocks, which have no interchangeable standard-cell drive variants and no Liberty-arc timing to score against. For analog / MS physical & integrity verification, see lvs (connectivity), layout (geometry), em-ir (IR / EM), thermal, and extract (RC).

Source & releases