Vyges Loom — the open EDA sign-off & optimization suite
The Loom suite, under
vyges. Install once —vyges install loom— then run any engine asvyges loom <engine>(e.g.vyges loom sta-si run top.sta). Each engine is also a standalonevyges-<engine>binary on your PATH, which is what the dispatch calls and the integration contract flow authors target directly (see integrating into a flow).
Commercial-grade engines — sign-off that analyzes and optimizers that
act on the result — each driven by a declarative job file that produces a
standard artifact. They share one cross-engine data spine (vyges-loom) — the
output of one is the input of the next, with no glue scripts:
.ext ─► vyges loom extract ─► .spef ──┐
.char ─► vyges loom char ─► .lib ──┼─► vyges loom sta-si ─► WNS / TNS ─► resize · vt-swap · buffer-insert ─► fixed netlist
└─► vyges loom power ─► activity ─┬─► vyges loom em-ir ─► IR-drop + EM
└─► vyges loom thermal ─► temp / hotspot
.gds + rules ─► vyges loom lvs ─► MATCH / MISMATCH
| Engine | Command | Job file | Output |
|---|---|---|---|
| char | vyges loom char | .char / .charlib | Liberty .lib |
| extract | vyges loom extract | .ext | SPEF |
| power | vyges loom power | .pwr | power report + activity map |
| sta-si | vyges loom sta-si | .sta | WNS / TNS / worst path |
| em-ir | vyges loom em-ir | .emir | IR-drop map + EM check |
| thermal | vyges loom thermal | .thermal | temperature field + hotspot |
| lvs | vyges loom lvs | .lvs | MATCH / MISMATCH + diagnostics |
Optimizers — they read the timer’s verdict and edit the netlist to fix it:
| Engine | Command | Job file | Output |
|---|---|---|---|
| resize | vyges loom resize | .resize | resized netlist (drive sizing) |
| vt-swap | vyges loom vt-swap | .vtswap | resized netlist (Vt / leakage) |
| buffer-insert | vyges loom buffer-insert | .bufins | buffered netlist (transition fix) |
Physical construction — they build the design database the engines above read. ⚠️ Not
part of vyges install loom: install the group with vyges install physical, or one with
vyges install <engine>. None has a published release yet, so vyges modules lists them as
unreleased and the installer says so rather than failing on a missing download.
| Engine | Command | Builds |
|---|---|---|
| ifp | vyges ifp | die area, core area and the standard-cell rows |
| mpl | vyges mpl | hard-macro placement, before the cells go round them |
| tap | vyges tap | well taps, endcaps, and row cutting around macros |
| pdn | vyges pdn | power rings, straps, follow pins and their vias |
| ppl | vyges ppl | IO pin slots and the assignment onto them |
| pad | vyges pad | the IO pad ring, bumps and RDL routes |
| dpl | vyges dpl | legal detailed placement, and the check for one |
| fin | vyges fin | density fill, to meet per-layer density rules |
Verification + utilities — prove correctness, or view the layout:
| Engine | Command | Input | Output |
|---|---|---|---|
| drc | vyges loom drc | GDS + .drc deck | geometry violations |
| cdc | vyges loom cdc | netlist + lib + SDC | clock-domain crossings |
| glitch | vyges loom glitch | netlist + Liberty | reconvergent-fanout hazards |
| lec | vyges loom lec | two netlists + lib | EQUIVALENT / NOT + counter-ex. |
| gds-view | vyges loom gds-view | GDS (+ marks) | layered SVG with overlay |
| opendb | vyges opendb <cmd> | .odb / .3dbx | ECO surgery, DEF I/O, 3D assembly checks |
opendb is the odd one out: it takes subcommands, not a job file, because it is the design database the other engines read and edit rather than an analysis over one. It is also the only engine with a native (C++/libodb) dependency, which is why the suite is unix-only.
Domain coverage. The suite is a digital sign-off / optimization flow; on top of that, lvs, layout, em-ir, thermal and extract additionally cover analog / mixed-signal physical & integrity verification — LVS, geometry, IR / EM, thermal, and RC. Analog functional / timing sign-off is out of scope.
Open core
Every engine is Apache-2.0 and runnable today. The per-foundry calibration plugins (NDA) stay private — the engine is open, the fab-specific accuracy is gated.
One declarative job in, one standard artifact out
No Tcl, no glue scripts: describe the job, get a standard sign-off file. The timing and power engines exit non-zero on a violation, so they gate CI directly. See job-file formats.