vyges-char — standard-cell characterization

Part of the Vyges Loom suite. Install once with vyges install loom, then run vyges loom char. It’s also a standalone vyges-char binary on your PATH (the integration contract for flow authors).

vyges-char generates a Liberty (.lib) timing & power library from SPICE models, orchestrating the SPICE runs in parallel from one declarative job file.

Run it

vyges install loom                            # one-time: fetch the Loom suite
vyges loom char demo                          # instant sample .lib (no sim)
vyges loom char run     inv.char -o inv.lib   # one cell → Liberty
vyges loom char library cells.charlib -o out/ # many cells, in parallel → merged .lib
vyges loom char check   inv.char              # validate the job

See the full CLI reference (generated from --help).

Where it sits

.char job in → .lib out. That .lib feeds vyges-sta-si, and its per-switch energy feeds vyges-em-ir. See the data spine.

Domain coverage

vyges-char produces Liberty standard-cell timing & power models — NLDM / CCS tables, timing arcs, slew × load delay surfaces — for a library of fixed-footprint logic cells. It is a digital sign-off input and does not apply to analog / mixed-signal blocks, whose behavior has no standard-cell or Liberty-arc analogue. For analog / MS physical & integrity verification, see lvs (connectivity), layout (geometry), em-ir (IR / EM), thermal, and extract (RC).

Source & releases

• Repo: https://github.com/vyges-tools/char
• Binaries: https://github.com/vyges-tools/char/releases
• Apache-2.0. Per-foundry calibration plugins are separate (NDA).