vyges-rmp — logic restructuring
Installed with the physical engines. Install it with
vyges install physical, then runvyges physical rmp. It is also a standalonevyges-rmpbinary on your PATH (the integration contract for flow authors). Source: vyges-tools/rmp.
vyges-rmp rebuilds the logic of a mapped, placed design for area or for delay. The logic is cut
out of the database as an and-inverter graph (AIG), re-synthesized, re-mapped onto the library’s
cells and written back in place. The AIG core is the one vyges-syn and vyges-lec use, so every
rewrite can be checked for equivalence against what it replaced.
The cut itself (the logic taken out, the round trip through ABC, the result put back) is
vyges-cut, a library vyges-rmp links.
| command | does |
|---|---|
restructure | the whole design’s logic re-synthesized for area, or for timing below a slack threshold |
resynth | the logic behind every end point with negative slack re-mapped for delay |
resynth-annealing | a simulated-annealing search over AIG rewrite sequences for the best worst slack |
resynth-genetic | a genetic search over the same sequences |
blif-write / blif-read | a set of instances out as a BLIF cut, and a BLIF’s gates back in their place |
Run it
vyges install physical # one-time
vyges physical rmp restructure placed.odb --liberty cells.lib --sdc top.sdc \
--liberty-file cells.lib --target area \
--tielo-port TIELO/Y --tiehi-port TIEHI/Y -o restructured.odb
vyges physical rmp resynth placed.odb --liberty cells.lib --sdc top.sdc -o resynth.odb
The timing commands time the design themselves, from the libraries, the constraints and the
placement’s wire estimate (--set-wire-rc). With more than one corner, --corners lists them
and --corner picks the one to optimize.
Events
Every command leaves a vyges-events trail on stderr: RMP-INPUT, RMP-REFUSED,
RMP-STEP (at debug) and RMP-DONE, which every command emits with its status and exit code.
-q raises the floor to error, -v lowers it to debug; an explicit VYGES_LOG wins.