vyges physical syn — CLI reference

Generated from vyges physical syn --help — this page is the tool’s own output, verbatim.

vyges physical syn — integrated logic synthesis from RTL to a mapped netlist, on the shared AIG core

USAGE:
  vyges physical syn run  <job>  RTL to a technology-mapped netlist
  vyges physical syn ir-normalize <in.ir> -o OUT.ir
                                  read a netlist in the IR text form, normalize it (topological
                                  order, dead logic dropped, loops broken) and write it back
  vyges physical syn sv-elaborate [--raw] [--liberty LIB]... -o OUT.ir <slang arguments...>
                                  elaborate SystemVerilog and write the netlist in the IR text
                                  form, cleaned up (library cells imported, constants folded);
                                  --raw: as the frontend built it, before any pass; --liberty:
                                  read a library, whose cells the design may instantiate
  vyges physical syn ir-pass [--liberty LIB]... <in.ir> -o OUT.ir PASS...
                                  read a netlist in the IR text form (its library cells imported),
                                  run the passes in order, write it back. PASS: normalize, opt,
                                  bitblast, bitblast-no-arith, liveness, abc-fraig, abc-dc2
                                  (the ABC round trips of synthesize), map-sequentials,
                                  map-combinationals, gate-fuse, stats (printed)
  vyges physical syn ir-pass [--liberty LIB]... -o OUT.ir PASS... --sv <slang arguments...>
                                  the same on the design as sv-elaborate leaves it, in memory
                                  (what the text form does not carry, register reset and clear
                                  values, kept)
  vyges physical syn synthesize [--liberty LIB]... [--lef LEF]... [--dont-use PATTERN]...
                                  -o OUT.v <slang arguments...>
                                  elaborate SystemVerilog, synthesize it onto the libraries' cells
                                  and write the mapped netlist as structural Verilog; the LEFs (the
                                  technology first) give the cells' masters; --dont-use withholds
                                  the cells it names (globs, whitespace-separated) from mapping
  vyges physical syn acd-resynth --liberty LIB... --sdc SDC [-o OUT.odb] [--verilog OUT.v] DESIGN.odb
                                  [--apply] [--effort E] [--max-leaves N] [--max-cells N]
                                  [--max-intermediate-leaves N] [--max-outerfans N]
                                  [--exclude-buffers] [--allow-lateral] [--name-index N]
                                  [--debug N] [--debug-acd N] [--trace]
                                  resynthesize the logic around each gate output failing timing
                                  from Ashenhurst-Curtis decompositions; --apply commits the
                                  substitutions (instances remap<N>, nets remap_net<N>, N from
                                  --name-index); --debug: the command's debug lines at that level;
                                  --trace: the call-sequence trace lines
  vyges physical syn --describe
  vyges physical syn --help
  vyges physical syn --version

OPTIONS:
  -o FILE               write the report (or the output database) to FILE
  --json                machine-readable output instead of the text report
  -q, --quiet           raise the causal trail's floor to error (VYGES_LOG)
  -v, --verbose         lower it to debug: each step of the command
                        (both go BEFORE the command: after it, -v is slang's)
  --describe            print a machine-readable JSON description of the command
  --bug-report          file a bug (central: vyges/community)
  --feature-request     request a feature (central)

EVENTS:
  The causal trail (vyges-events JSON lines) goes to stderr; netlists, reports and log lines go
  to stdout or -o. SYN-INPUT, SYN-REFUSED, SYN-STEP (debug) and SYN-DONE (every command: its
  status and exit code). An explicit VYGES_LOG wins over -q and -v.

EXIT STATUS:
  0  ok
  1  a finding — the check ran and failed
  2  usage or unreadable input
  3  refused — this build does not implement the command yet

Contract

Generated from vyges physical syn --describe.

syn

Integrated logic synthesis from RTL to a mapped netlist, on the shared AIG core.

Maturity: discovered

synthesize --liberty {liberty} --lef {tech_lef} --lef {cell_lef} -o {out} {rtl}

Consumes: rtl, liberty, lef

Artifacts: netlist (out)

Assertion: syn-synthesized — none; this operation establishes no engineering claim

Provenance limitations

• ir-normalize, sv-elaborate, ir-pass, synthesize and acd-resynth are built; run refuses with exit 3.
• acd-resynth times one scene without wire parasitics.
• The described call is synthesize: one SystemVerilog source elaborated, synthesized onto one Liberty’s cells and written as structural Verilog. The technology LEF and the cell LEF are required: without a technology the export to the database stops (SYN-0033).
• synthesize prints its log and writes the netlist; it has no –json output (a –json is read as an elaborator argument and elaboration fails), so emits_json is false and the result is the printed log.
• Every argument after the first source is passed to the elaborator, so only an elaborator option (top) can follow it. More than one source, Liberty or cell LEF, include directories and defines need the engine’s own arguments.
• Synthesis establishes no claim about the design: the assertion is not_applicable. A design that does not elaborate or map exits 1 with its error line printed and writes no netlist.
• input_hash covers the argument vector, not the content of the source, Liberty or LEF files it names, nor any file the source includes.