vyges physical rmp — CLI reference
Generated from vyges physical rmp --help — this page is the tool’s own output, verbatim.
vyges physical rmp — logic restructuring on an AIG: re-synthesis of timing-critical or area-heavy logic, with every rewrite checkable for equivalence
USAGE:
vyges physical rmp run <design.odb> <job> -o OUT.odb re-synthesise a region for area or delay
vyges physical rmp blif-write <design.odb> --liberty FILE... --inst NAME... -o OUT.blif
[--const0 CELL PORT] [--const1 CELL PORT]
the instances as a BLIF cut
vyges physical rmp blif-read <design.odb> --liberty FILE... --inst NAME... --blif FILE -o OUT.odb
[--const0 CELL PORT] [--const1 CELL PORT] [--call-id N]
replace the instances by the BLIF's gates
vyges physical rmp restructure <design.odb> --liberty FILE... --sdc FILE --liberty-file FILE -o OUT.odb
[--target area|timing] [--tielo-port CELL/PORT] [--tiehi-port CELL/PORT]
[--work-dir DIR] [--abc-logfile FILE] [--slack-threshold S] [--depth-threshold N]
[--set-wire-rc "ARGS"] [--routing-alpha A]
the design's logic re-synthesised through ABC
(--set-wire-rc: the placement estimate's wire RC)
vyges physical rmp resynth <design.odb> --liberty [CORNER=]FILE... --sdc FILE -o OUT.odb
[--corners A,B,...] [--corner C] [--name-index N]
[--dont-use PAT] [--unset-dont-use PAT] [--reset-dont-use]
[--set-wire-rc "ARGS"] [--routing-alpha A]
the logic behind every negative-slack end point
re-mapped by ABC for delay (the dont-use options
apply in order after the Liberty dont_use cells)
vyges physical rmp resynth-annealing <design.odb> (resynth's options)
[--iters N] [--revert-after N] [--seed S] [--temp T] [--initial-ops N]
[--slack-threshold S]
a simulated-annealing search over AIG rewrite
sequences for the corner's best worst slack
vyges physical rmp resynth-genetic <design.odb> (resynth's options)
[--iters N] [--seed S] [--population-size N] [--mutation-probability P]
[--crossover-probability P] [--tournament-size N]
[--tournament-probability P] [--initial-ops N] [--slack-threshold S]
a genetic search over the same sequences
vyges physical rmp --describe
vyges physical rmp --help
vyges physical rmp --version
OPTIONS:
-o FILE write the report (or the output database) to FILE
--json machine-readable output instead of the text report
-q, --quiet raise the causal trail's floor to error (VYGES_LOG)
-v, --verbose lower it to debug: each step of the command
--describe print a machine-readable JSON description of the command
--bug-report file a bug (central: vyges/community)
--feature-request request a feature (central)
EVENTS:
The causal trail (vyges-events JSON lines) goes to stderr; reports and log lines go to stdout.
RMP-INPUT, RMP-REFUSED, RMP-STEP (debug) and RMP-DONE (every command: its status and exit
code). An explicit VYGES_LOG wins over -q and -v.
EXIT STATUS:
0 ok
1 a finding — the check ran and failed
2 usage or unreadable input
3 refused — this build does not implement the command yet
Contract
Generated from vyges physical rmp --describe.
rmp
Logic restructuring on an AIG: re-synthesis of timing-critical or area-heavy logic, with every rewrite checkable for equivalence.
Maturity: discovered
restructure {design} --liberty {liberty} --liberty-file {liberty} --sdc {sdc} -o {out}
| Input | Type | Required | Description |
|---|---|---|---|
design | string | yes | design database (.odb) to restructure |
liberty | string | yes | Liberty library (.lib): timed against and mapped onto |
sdc | string | yes | timing constraints (.sdc) |
out | string | yes | database (.odb) to write |
target | string | no | optimise for area (default) or timing |
tielo_port | string | no | tie-low cell output as CELL/PORT, e.g. LOGIC0_X1/Z |
tiehi_port | string | no | tie-high cell output as CELL/PORT, e.g. LOGIC1_X1/Z |
depth_threshold | integer | no | timing target: the first end point whose worst path is deeper than this many levels is restructured (default 16) |
work_dir | string | no | directory for the intermediate BLIF and ABC files (default: the working directory) |
abc_logfile | string | no | file to write ABC’s log to |
Consumes: odb, liberty, sdc
Artifacts: odb (out)
Assertion: rmp-restructured — none; this operation establishes no engineering claim
Provenance limitations
blif-writeandblif-readare built (the cut’s BLIF, arrivals and requireds not written);restructure(both targets),resynth,resynth-annealingandresynth-geneticare built;runrefuses with exit 3.- restructure matches the reference at pin 27288f5 on 3 of 3 regression cases (area and timing targets): the database (Verilog and DEF), the cut BLIF with its arrival and required times, and the log, byte for byte.
- resynth matches the reference at pin 27288f5 on 10 of 10 regression calls, and resynth-annealing and resynth-genetic on 5 of 5: the database (Verilog and DEF) and the log, byte for byte.
- The described call is
restructure: the design’s logic re-synthesised through ABC for area (the default) or timing, and the database written toout. One Liberty is both timed and mapped onto (--libertyand--liberty-filetake the same file); more libraries, a wire RC estimate and the resynth commands need the engine’s own arguments. restructureprints its log and writes the database; it has no –json output (a –json is refused as an unknown option, exit 2), so emits_json is false and the result is the printed log.- Restructuring establishes no claim about the design: the assertion is not_applicable. Without both tie cells (
tielo_port,tiehi_port) cells with constant outputs are not removed, and a warning is printed for each one not given.--slack-thresholdis accepted and has no effect onrestructure, so it is not described. Intermediate files go towork_dir, the working directory when it is not given. - input_hash covers the argument vector, not the content of the database, Liberty or SDC it names.