vyges-power — power analysis

Part of the Vyges Loom suite. Install once with vyges install loom, then run vyges loom power. It’s also a standalone vyges-power binary on your PATH (the integration contract for flow authors).

vyges-power computes a design’s power — leakage, internal, and switching — from a gate-level netlist and the Liberty models, using either a measured activity file (VCD) or a vectorless probabilistic toggle factor. It also emits the per-instance activity / current map that vyges-em-ir consumes, so IR-drop is solved from real per-instance current — closing the char → power → em-ir loop.

Run it

vyges install loom                              # one-time: fetch the Loom suite
vyges loom power demo                            # instant: built-in design → power report
vyges loom power run  block.pwr                  # leakage + internal + switching report
vyges loom power run  block.pwr --fail-on-budget # exit 3 over the job's power budget (CI gate)
vyges loom power check block.pwr                 # validate the job

See the full CLI reference (generated from --help).

Where it sits

Netlist + .lib + activity (VCD or vectorless) → a power report, plus the activity map em-ir reads. It can also read extracted wire caps (.spef) from vyges-extract for switching power. Designed to gate CI: over-budget returns a distinct non-zero exit code. See the data spine.

Domain coverage

vyges-power sums per-cell Liberty leakage and internal energy weighted by toggle activity over a gate-level netlist — it is digital sign-off. It does not apply to analog / mixed-signal blocks, whose power has no standard-cell or Liberty analogue (an analog block’s operating-point current is an input to em-ir, not something this engine computes). For analog / MS physical & integrity verification, see lvs (connectivity), layout (geometry), em-ir (IR / EM), thermal, and extract (RC).

Source & releases

• Repo: https://github.com/vyges-tools/power
• Binaries: https://github.com/vyges-tools/power/releases
• Apache-2.0.