vyges-syn — logic synthesis
Installed with the physical engines. Install it with
vyges install physical, then runvyges physical syn. It is also a standalonevyges-synbinary on your PATH (the integration contract for flow authors). Source: vyges-tools/syn.
vyges-syn takes SystemVerilog to a gate-level netlist on your library’s cells. It works on the
same and-inverter graph (AIG) core as vyges-rmp and vyges-lec, so a flow can go from RTL to a
placed design, and check every step, without leaving the suite.
What synthesize does, in order:
| stage | does |
|---|---|
| elaborate | the SystemVerilog frontend builds the design; library cells it instantiates are imported, constants folded |
| bit-blast | words become bits, arithmetic kept for the optimizer and lowered after it |
| liveness | registers and logic that reach no output are removed |
| optimize | two AIG optimization rounds (functional reduction, then rewriting for depth and area) |
| map registers | each register onto a flip-flop cell, with its reset and enable |
| map logic | the combinational logic onto the library’s gates, matched by function |
| gate fusion | neighbouring gates merged into a larger cell wherever that saves area |
| export | ports, instances and nets into the design database, written as structural Verilog |
Run it
vyges install physical # one-time
vyges physical syn synthesize --liberty cells.lib \
--lef tech.lef --lef cells.lef -o top.v -- top.sv --top top # RTL -> netlist
The LEFs give the cells their masters in the database; the technology LEF comes first. Every
argument after -- goes to the SystemVerilog frontend (files, --top, -I, -D, …).
The stages also run one at a time, on the netlist in a readable text form, which is how a flow inspects what one pass did:
vyges physical syn sv-elaborate --liberty cells.lib -o top.ir -- top.sv
vyges physical syn ir-pass --liberty cells.lib top.ir -o mapped.ir bitblast abc-dc2 map-combinationals stats
Timing-driven resynthesis
acd-resynth works on a netlist already linked into the design database. It times the design
against your constraints, and around each gate output that fails timing it looks for a faster
rewrite of the surrounding logic, built from Ashenhurst-Curtis decompositions on your library’s
cells. Each failing output keeps its best candidate. --apply commits them all in one step, and
the result can be written back as a database and as structural Verilog:
vyges physical syn acd-resynth --liberty cells.lib --sdc top.sdc --apply \
-o top-resynth.odb --verilog top-resynth.v top.odb
--max-leaves, --max-cells, --max-outerfans and --effort bound the search. --debug 1
prints each output’s best rewrite, with its gain and the area before and after.
What it reports
The run prints a statistics table of the mapped design (cells by type, area) and one line per
export: instances, nets and ports created. A design that cannot be synthesized stops with an
[ERROR SYN-nnnn] line and exit 1; unreadable input is exit 2; a command not built yet is
refused with exit 3.
Events
Every command leaves a vyges-events trail on stderr: SYN-INPUT, SYN-REFUSED,
SYN-STEP (at debug) and SYN-DONE, which every command emits with its status and exit code.
-q raises the floor to error and -v lowers it to debug; both go before the command, since
what follows it belongs to the SystemVerilog frontend. An explicit VYGES_LOG wins.