vyges-remap — multi-output technology re-mapping

Part of the Vyges Loom suite. Install once with vyges install loom, then run vyges loom remap. It’s also a standalone vyges-remap binary on your PATH (the integration contract for flow authors).

vyges-remap answers: can this netlist be mapped better using cells a single-output mapper cannot reach? Given an AIGER netlist (or Verilog RTL, from which Yosys extracts one) and a technology genlib, it runs a single-output baseline and a multi-output pass, writes the remapped Verilog, and reports the before/after cell and area delta — including how many multi-output cells (adders, compressors) were mapped that a single-output mapper would have missed.

Run it

vyges install loom                                                   # one-time
vyges loom remap emap --verilog design.v --top top --genlib cells.genlib -o mapped.v

Every remap is gated by an equivalence check

A transform that changes the netlist has to prove it did not change the function. After mapping, remap runs an ABC combinational equivalence check of the mapped netlist against the input AIG. A failed check makes the run an error, and the netlist is rejected rather than handed on.

The verdict is tri-state, and the middle state matters:

null resolves to unknown in the result envelope. A remap that was not checked is not a remap that is correct — nothing has established that the mapped netlist still computes the input function, and a consumer reading only the execution status would see ok for an unverified transform. That conflation is exactly what the two status axes exist to prevent.

Provenance

The mapping and the equivalence check are performed by external emap, abc and yosys binaries resolved at run time. Their versions are not part of input_hash, so the same arguments can produce a different result under a different toolchain build — the engine declares this in its descriptor, and it travels with every result as provenance.limitations.