vyges-remap — CLI reference
Generated from vyges-remap --help. Do not edit by hand — run scripts/gen-cli-reference.sh.
vyges-remap — file-level multi-output technology re-mapping (mockturtle emap)
usage:
vyges-remap emap (--verilog <d.v> --top T | --aig <a.aig>) (--genlib <g> | --liberty <lib>) [-o out.v] [--no-cec] [--json]
vyges-remap --describe structured tool contract (for `vyges mcp`)
vyges-remap --version | --help
Extracts an AIG (Yosys, from --verilog) or takes one (--aig), then runs the
vyges-emap driver twice (single-output baseline + multi-output) and reports the
before/after cell/area delta. Tools resolve via $VYGES_EMAP / $VYGES_YOSYS / $VYGES_ABC.
Contract
Generated from vyges-remap --describe.
remap
File-level multi-output technology re-mapping (mockturtle emap): AIGER + genlib -> mapped netlist + before/after cell/area delta.
Maturity: structured
emap --verilog {verilog} --top {top} --genlib {genlib}
| Input | Type | Required | Description |
|---|---|---|---|
aig | string | no | alternative to verilog: a pre-made AIGER netlist |
genlib | string | yes | technology genlib (multi-output cells are derived from xor/maj gates) |
out | string | no | path to write the remapped Verilog netlist |
top | string | yes | top module name |
verilog | string | yes | Verilog RTL of the logic to remap (Yosys extracts the AIG) |
Artifacts: netlist (out_netlist)
Assertion: remap-equivalent — passes when equivalent is true
Provenance limitations
- input_hash covers the argument vector, not the content of the Verilog, AIGER or genlib it names.
- The mapping and the equivalence check are performed by external emap/abc/yosys binaries resolved at run time; their versions are not part of input_hash, so the same arguments can produce a different result under a different toolchain build.