vyges loom est — CLI reference

Generated from vyges loom est --help — this page is the tool’s own output, verbatim.

vyges loom est — parasitic estimation: the RC network of every placed net, as SPEF

USAGE:
  vyges loom est estimate <job.json> [-o FILE]
  vyges loom est --describe
  vyges loom est --help
  vyges loom est --version

JOB FIELDS:
  steps     required — the commands in order, each {"cmd": ..., "args": [...]}:
              read_lef, read_def, read_db, read_liberty [-corner c], define_corners,
              create_clock [-name N] <sources>, set_propagated_clock <objects>,
              set_clock_latency <objects> (per clock and pin: an ideal clock's nets
              get no network), set_layer_rc, set_wire_rc,
              estimate_parasitics [-placement] [-spef_file F] (no flag: the source is
                picked as the reference does, placement here; unplaced is EST-0009, no
                wire capacitance EST-0014)
  alpha     the Steiner builder's Prim-Dijkstra alpha (default 0.3)
  trace     write the RC state and one decision line per net to this path

OPTIONS:
  -o FILE               write the JSON report to FILE instead of stdout
  --json                accepted; the report is JSON either way
  --describe            print a machine-readable JSON description of the command
  --bug-report          file a bug (central: vyges/community)
  --feature-request     request a feature (central)
  --sponsor             sponsor Vyges (github.com/sponsors/vyges-ip)
  --star                star this tool on GitHub

EXIT STATUS:
  0  estimated    at least one net was estimated and every requested SPEF was written
  2  vacuous      no net was estimated — no estimate step, or every corner lacked wire
                  capacitance (EST-0018). NOT a pass.
  2  error        usage, unreadable input, or a step that failed
  3  refused      a step or an option this engine does not model — see `reason`

Contract

Generated from vyges loom est --describe.

est

parasitic estimation from placement: a Steiner tree per net, its RC network per corner, written as SPEF

Maturity: structured

estimate {job}

Consumes: job

Artifacts: spef (spef_files)

Assertion: parasitics-estimated — passes when status equals estimated

Provenance limitations

• input_hash covers the argument vector, not the content of the job file or of the design files it names.
• status is one of estimated, vacuous, refused or error. VACUOUS IS NOT ESTIMATED: no net was estimated, either because no estimate step ran or because every corner lacked signal wire capacitance (EST-0018, where the reference estimates nothing either). The declared assertion passes only on estimated. Exit status is 0 for estimated, 2 for vacuous and for error, 3 for refused.
• Correlated against the reference at pin 27288f5c90265ae5296b2f5a9fa6e8714fa191ad, 2026-10-12, comparing every SPEF byte for byte against a fresh reference run: 9 of 9 cases of the reference’s own estimate_parasitics -placement tests with 0 differing lines, and 191 of 192 cases across the rest of its regression suite that call it, 22,484 nets exact; the one corpus case not scored fails while the reference prepares it. Earlier, at pin da9f29f18b6487825aa880597176e0fa97110b31, 2026-10-02, comparing every SPEF byte for byte against a fresh reference run: 9 of 9 cases of the reference’s own estimate_parasitics -placement tests, and 185 of 186 cases across the rest of its regression suite that call it, 21,637 nets, 0 differing lines; the one corpus case not scored fails in the reference itself. The logic simulation that decides constant drivers matches the reference reading the same database pin for pin on every one of those designs. A NUMBER HERE MEANS NOTHING WITHOUT THE BUILD: the pin is part of the claim.
• Only the placement source is modelled: -placement, and estimate_parasitics with no flag, which picks the source as the reference does (placement for a job, which runs no router; a database holding global routes is refused) and raises the reference’s errors for an unplaced design (EST-0009) and missing wire capacitance (EST-0014). estimate_parasitics -global_routing is refused as a command; the library’s global-route network (the wire module) is used by the router, not by this command.
• REFUSED rather than approximated: liberty latch_bank groups; set_case_analysis, set_logic_*, set_disable_timing, create_generated_clock, set_sense and set_clock_sense, which change which pins are clocks without touching the database.
• Units, cell clock pins and constant outputs come from the FIRST liberty library read, as the timer’s do. RC commands before any liberty read are refused: the timer’s default units are not modelled. set_wire_rc checks its selectors before that, as the reference does: both -tech and -redistribution_layer (EST-0028) or an unknown -tech (EST-0030) is an error, and -redistribution_layer alone is refused (RDL chips are not modelled).
• Every value is single precision where the reference’s is: Tcl doubles are narrowed to float at the command boundary, resistances and capacitances are summed as float, and SPEF values are printed as %g with six significant digits after a float division by the unit scale.
• The Steiner tree is built by vyges-stt, which is correlated separately.