vyges physical cts — CLI reference

Generated from vyges physical cts --help — this page is the tool’s own output, verbatim.

vyges physical cts — clock tree synthesis of a placed design: the clock buffers chosen, each clock
net found and its sinks collected (the trees themselves are not built yet)

USAGE:
  vyges physical cts clock_tree_synthesis <job.json> [-o FILE]
  vyges physical cts --describe
  vyges physical cts --help
  vyges physical cts --version

JOB FIELDS:
  steps        required — the commands in order, each {"cmd": ..., "args": [...]}, as a flow
               script passes them: read_db, read_liberty, set_wire_rc, set_layer_rc,
               set_dont_use, set_debug_level, set_mode, read_sdc, set_cts_config, set_max_fanout,
               then clock_tree_synthesis [options]
  write_def    optional — where to write the design as DEF when the command is done
  write_db     optional — where to write the design as a database when the command is done

MODELLED:
  the buffer list (given, or inferred from the libraries), the root, sink and characterization
  buffers, clock-gate cloning, every clock net and its sinks, the characterization, each net's
  H-tree (sink clustering, simple segments, the obstruction-aware legalizer, macro and register
  trees), the trees written with their dummy loads and clock NDRs, the per-tree report, and the
  latency balancing of trees with sub-trees — the report's lines are the command's own, in its
  order.
  Not yet: -repair_clock_nets, hierarchical designs, clock buffer strings and footprints.

OPTIONS:
  -o FILE               write the JSON report to FILE instead of stdout
  --json                accepted; the report is JSON either way
  --describe            print a machine-readable JSON description of the command
  --bug-report          file a bug (central: vyges/community)
  --feature-request     request a feature (central)
  --sponsor             sponsor Vyges (github.com/sponsors/vyges-ip)
  --star                star this tool on GitHub

EXIT STATUS:
  0  done         the clock trees were built, written to the design and reported
  0  up_to_date   clock nets were looked for and none was found: nothing to build
  2  vacuous      the job has no clock_tree_synthesis step. NOT a pass.
  2  error        usage, unreadable input, or an error the command raises (its line is reported)
  3  refused      an input or a stage this engine does not model — see `reason` (and
                  `modelled_through` when the trees were built but not written)

Contract

Generated from vyges physical cts --describe.

cts

clock tree synthesis of a placed design: clock buffers chosen, clock nets found, an H-tree built per net and written with its dummy loads

Maturity: structured

clock_tree_synthesis {job}

Consumes: job

Assertion: clock-trees-built — passes when status is one of done, up_to_date

Provenance limitations

• input_hash covers the argument vector, not the content of the job file or of the design files it names.
• status is one of done, up_to_date, vacuous, refused or error. done means the trees were built, written and reported; up_to_date means clock nets were looked for and none was found. A run that needs a stage not yet modelled (sink clustering, clock NDRs, clock-net repair, latency balancing of sub-trees) is refused, with modelled_through: htree when the trees were built but not written. The declared assertion passes on done and up_to_date. Exit status is 0 for done and up_to_date, 2 for vacuous and for error, 3 for refused.
• Modelled: buffer list inference, root/sink/characterization buffer selection, clock-gate cloning, clock-net discovery through gaters and bidirect pads. Refused rather than guessed: hierarchical designs where a clone or register-tree buffer is made, insertion-delay (clock-tree-path) cells, several corners, set_disable_timing, case analysis and generated clocks.