vyges-ppl — IO pin placement

Physical construction — opt-in, and not part of vyges install loom. These engines build the design database that the sign-off and verification engines read, so they install as their own group:

vyges install physical   # all six
vyges install ppl        # just this one

It is also a standalone vyges-ppl binary on your PATH, which is what the dispatch calls and what a flow author targets directly. Source: vyges-tools/ppl.

vyges-ppl decides where a block’s IO pins sit on its boundary. It builds the legal slots from the routing tracks on each layer, then assigns pins onto them to minimise the wire needed to reach them — honouring constraints, groups, exclusions and fixed pins.

Run it

vyges ppl place-pins design.odb --hor-layers metal3 --ver-layers metal2
vyges ppl slots      design.odb --hor-layers metal3 --ver-layers metal2   # inspect the lattice

Where it sits

Floorplanned database in, placed pins out. It runs against the same rows and die that ifp created, and its result is what a router later has to reach.

Known bounds

• The annealing placement path is not reproduced; the deterministic (Hungarian) assignment is. Cost-equal ties may place a pin at a different legal position than the reference chose, which is a tie rather than a shortfall.
• Constraints live in the database, not the command line — set_io_pin_constraint writes them onto the ports, and this engine reads them from there.

See the full CLI reference (generated from --help and --describe).