vyges-glitch — static glitch / hazard analysis

Part of the Vyges Loom suite. Install once with vyges install loom, then run vyges loom glitch. It’s also a standalone vyges-glitch binary on your PATH (the integration contract for flow authors).

vyges-glitch finds reconvergent-fanout hazards — the spots where one signal reaches a combinational endpoint by more than one path and can momentarily glitch before it settles. That is exactly what a lockstep gate-level simulator cannot see: it samples one settled value per tick and steps over the intermediate glitch. Catching it is a structural + timing question — parity from each Liberty arc’s timing_sense, the glitch window from the same delay tables vyges-sta-si uses.

Run it

vyges install loom                                              # one-time
vyges loom glitch check design.v --lib cells.lib                 # -> hazard report
vyges loom glitch check design.v --lib cells.lib --fail-on-violation   # exit 3

A source reaching an endpoint by ≥2 paths is flagged static (the paths differ in inversion parity, so a single edge can drive the endpoint the wrong way for a moment) or dynamic (same parity, different delay — a glitch over the settling window). A balanced reconvergence is not flagged.

See the full CLI reference (generated from --help).

Where it sits

Netlist + Liberty → hazards (text or --json, with a CI exit code). It fills the glitch blind spot of simulation and leans on the same timing data the STA engine uses. SAT/BDD path sensitization and function hazards are the depth passes.