vyges-cdc — clock-domain-crossing check

Part of the Vyges Loom suite. Install once with vyges install loom, then run vyges loom cdc. It’s also a standalone vyges-cdc binary on your PATH (the integration contract for flow authors).

vyges-cdc finds the spots where a signal launched in one clock domain is captured in another, and checks each is properly synchronized. It is a purely structural graph analysis — which signals cross domains, and through what? — and notably a question a lockstep gate-level simulator structurally cannot answer. It assigns each flop a domain by tracing its clock pin to an SDC clock source, walks each capture flop’s data cone to its launch flops, and reports every cross-domain pair.

Run it

vyges install loom                                                  # one-time
vyges loom cdc check design.v --lib cells.lib --sdc design.sdc       # -> crossings report
vyges loom cdc check design.v --lib cells.lib --sdc design.sdc --fail-on-violation  # exit 3

Each create_clock in the SDC is a clock domain; the Liberty identifies the flops and their clock/data pins. A crossing is OK when it is a clean two-flop synchronizer, and a violation when there is no synchronizer or combinational logic sits on the crossing path.

See the full CLI reference (generated from --help).

Where it sits

Netlist + Liberty + SDC → the list of domain crossings (text or --json, with a CI exit code). It’s an early structural lint that complements simulation — the crossings sim can’t see. Handshake / gray-code recognition and reconvergence are the depth passes.